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Copper Pillar Bump

Category Description :

Copper pillar bump technology is to produce a bump on the surface of wafer. It is an advanced interconnection technology for chip to chip, chip to substrate and chip to interposer flip-chip bonding. It can offer advantages in high current, good electromigration performance, excellent heat conductivity and ROHS/ Green compliance. It is an excellent interconnect solution for fine pitch and high performance chips, such as high speed Transceivers, RF PA, Embedded Processors, Application Processors, Power Management IC, Baseband, ASICs, and SOCs.


Process flow

Process Specifications:

Feature

Description

Wafer size

300mm/200um

Pillar Height

40~100um

Pillar pitch (Min)

80um

RDL

Yes

Polyimide

Yes

ROHS/Green

Yes

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